In present technology, a typical pin grid array for a complex semiconductor chip may include for example 296 pins, many of which are connected by a trace to a bond finger, each such bond finger being connectable to a pad on the chip by means of a wire bond.
The traces may be on different levels and may be appropriately connected by vias so that proper connection between a pin and a bond pad is achieved in a relatively compact package.
As is well known, it is important to electrically characterize the pin grid array itself, without the die in place. In furtherance thereof, a number of parameters of the pin grid array, such as input/output resistance, inductance, and capacitance, and power/ground, resistance, and capacitance must be measured.
A general description of such characterization is provided in the document "JEDEC STANDARD PROPOSAL LCZ MEASUREMENT METHOD", dated May 17, 1995, pages 1-20.
Typically, the electrical characterization of a pin grid array has been undertaken by first cutting off all the pins of the array, leaving the base of each pin exposed and substantially flush with the surface of the package material. Next, a body of solder is applied to all the exposed bases of the pins to short them together. Then, a small area of solder is melted and a vacuum gun is applied to draw some solder away so that a single pin base is exposed and no longer shorted to all the other pin bases. Electrical probes are then applied to the solder and exposed pin base respectively and electrical characterization tests are undertaken.
Then, in order to gain further characterization information of the pin grid array, the exposed pin base is again covered with solder to short it to all the other pin bases, and another area of the solder is melted and vacuumed away to provide that another pin base is exposed and not shorted to the other pin bases. The newly exposed pin base and solder are then probed and electrical tests are undertaken to gain further characterization information of the pin grid array.
This format is repeated in a wide variety of configurations in furtherance of achieving full pin grid array characterization.
In view of the large number of pin combinations that must be probed and tested in various ways to achieve complete device characterization, it is typical that for an array of this size, complete characterization may take, for example, one man-month to achieve.
In addition, using solder and a vacuum gun to achieve isolation of a pin base (or pin bases) is obviously unwieldy and also dangerous due to the heat involved in melting the solder and the fumes given off thereby.